1. Field of the Invention
The present invention relates to a semiconductor device which withstands a high voltage, for example, an IGBT (Insulating Gate Bipolar Transistor).
2. Description of the Related Art
FIG. 18A shows a conventional vertical IGBT of a punch-through type. In the IGBT 10, an n+-type buffer layer (hereinafter referred to as the n+ buffer layer) 12 and an nxe2x88x92-type high resistance layer (hereinafter referred to as the nxe2x88x92 high resistance layer) 13 are formed by epitaxial growth on a p+ substrate 11. A p-type base layer 14 is formed in a surface region of the nxe2x88x92 high resistance layer 13. An n+ source region (cathode) 15 is formed in a surface region of the base layer 14. A trench-type gate electrode 16 is formed in the source region 15, the base layer 14 and the nxe2x88x92 high resistance layer 13. The gate electrode 16 is insulated from the source region 15, the base layer 14 and the nxe2x88x92 high resistance layer 13 by a gate insulating film 17.
The IGBT 10 is produced with, for example, an epitaxial substrate, on which an epitaxial layer is formed in advance. However, the epitaxial substrate is disadvantageous in that the cost for manufacturing an element is high since the wafer is expensive.
Further, in the aforementioned IGBT 10, the substrate 11, which is relatively thick, is used as a p+ drain layer (anode). Therefore, to lower the carrier injection efficiency, it is necessary to control the lifetime. Typically, a process for shortening the lifetime of 5-10 xcexcs to about 100 ns is performed. As a result, a high-speed turn-off characteristic can be obtained, although the process has a drawback that the on-state voltage rises. This is because the carrier density in the nxe2x88x92 high resistance layer 13 is lowered by shortening the lifetime.
On the other hand, the on-state voltage can be lower if the lifetime is not shortened. However, in this case, the turn-off time will be considerably long. Thus, there is a tradeoff relationship between the on-state voltage and the turn-off time.
Further, a depletion layer extends from the base layer 14 due to a voltage applied to the element when the current is turned off. When the depletion layer reaches the n+ buffer layer 12, it is immediately stopped. For this reason, the drain current is instantaneously dropped to zero, so that the drain voltage oscillates, resulting in generation of noise.
FIG. 18B shows another conventional IGBT, in which the characteristic of the element described above is improved. The IGBT 20 shown in FIG. 18B has a p+ anode structure injected with a small amount of impurities at a low dose, which is adopted in a non-punch-through IGBT. Therefore, the operation speed can be increased without controlling the lifetime. The IGBT 20 comprises an n-type buffer layer (hereinafter referred to as the n buffer layer) 23 formed between the nxe2x88x92 high resistance layer 21 and the p+ drain layer (anode) 22. The n buffer layer 23 maintains the static breakdown voltage.
In this structure, the drain layer 22 must be injected with impurities at a low dose but have such a high concentration in the surface portion thereof that can establish ohmic contact. Therefore, the region where the impurities injected to form the drain layer 22 are diffused must be limited to a very shallow depth. The total thickness of the IGBT is equal to the thickness of the nxe2x88x92 high resistance layer 21, which is determined in accordance with the static breakdown voltage, plus the thickness of the n buffer layer 23 and the p+ drain layer 22. More specifically, in the case of an element of the 600V voltage series, the total thickness is as small as about 60 xcexcm.
Thus, the element is very thin. Therefore, for example, when the element is lapped, if the thickness is thinner or thicker than the design value by several microns, the thickness of the buffer layer 23 is varied. The variation in thickness of the buffer layer 23 is reflected on a variation in dose into the buffer layer 23, with the result that the characteristics of the element are considerably influenced. Therefore, when the element is manufactured, it is necessary to finish the element to the designed thickness with a minimum error. However, according to the current lapping technique, the lapping error is xc2x15 to 10 xcexcm, which is significantly large relative to the overall thickness of 60 xcexcm.
As described above, in the conventional vertical IGBTs, there is a tradeoff relationship between the on-state voltage and the turn-off time. Therefore, in the IGBT of the punch-through type using a thick p+ substrate as a p+ anode, since lifetime control is inevitable, there is a limit to reduction in ON characteristic. In the IGBT of the non-punch-through type in which the static breakdown voltage is maintained by the n buffer layer 23 formed between the p+ drain layer 22 and the nxe2x88x92 high resistance layer 21, the element must be very thin. However, this type of IGBT is disadvantageous in that the lapping error is large and the element characteristic is varied considerably. Therefore, there is a demand for a semiconductor device which has an element having required turn-off time and ON characteristic using a thin substrate and which can suppress the influence of the lapping error on the element characteristic.
According to an aspect of the present invention, there is provided a semiconductor device comprising:
a first buffer layer of a first conductivity type; a high resistance layer of the first conductivity type formed on the first buffer layer; a base layer of a second conductivity type formed on the high resistance layer; a source region of the first conductivity type in a surface region of the base layer; a gate electrode insulated from the source region, the base layer and the high resistance layer; a drain layer of the second conductivity type formed on an opposite side of the first buffer layer from a surface on which the high resistance layer is formed; and a second buffer layer of the first conductivity type formed between the first buffer layer and the drain layer, an impurity concentration of the second buffer layer being higher than that of the first buffer layer.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a high resistance layer of a first conductivity type on a main surface of a first buffer layer of the first conductivity type, an impurity concentration of the high resistance layer being lower than that of the first buffer layer; forming a base layer of a second conductivity type in a surface region of the high resistance layer; forming a source region of the first conductivity type in a surface region of the base layer; forming a gate electrode insulated from the source region, the base layer and the high resistance layer; lapping a rear surface of the first buffer layer; injecting impurities through the rear surface of the first buffer layer, thereby forming a second buffer layer of the first conductivity type, an impurity concentration of the second buffer layer being higher than that of the first buffer layer; and forming a drain layer of the second conductivity type on a rear surface of the second buffer layer.